The present disclosure relates to semiconductor devices and methods for fabricating the same.
Multi-gate transistors may be one of several possible scaling technologies that can be used to increase the density of semiconductor devices. In multi-gate transistors, silicon bodies in a fin or nanowire shape may be formed on a substrate, with gates being formed on surfaces of the silicon bodies.
Such multi-gate transistors can be more easily scaled, as they may use a three-dimensional channel. Further, current control capability can be enhanced without increasing the gate lengths of the multi-gate transistors. Furthermore, may be possible to effectively suppress short channel effect (SCE), which may refer to a phenomenon whereby the electric potential of the channel region is influenced by the drain voltage.